Details
Complete Symbolic Simulation of SystemC Models
Efficient Formal Verification of Finite Non-Terminating ProgramsBestMasters
|
53,49 € |
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| Verlag: | Springer Vieweg |
| Format: | |
| Veröffentl.: | 16.03.2016 |
| ISBN/EAN: | 9783658126803 |
| Sprache: | englisch |
Dieses eBook enthält ein Wasserzeichen.
Beschreibungen
<p>In his
master thesis, Vladimir Herdt presents a novel approach, called complete
symbolic simulation, for a more efficient verification of
much larger (non-terminating) SystemC programs. The
approach combines symbolic simulation with stateful model checking and allows
to verify safety properties in (cyclic) finite state spaces, by exhaustive
exploration of all possible inputs and process schedulings. The state explosion
problem is alleviated by integrating two complementary reduction techniques. Compared
to existing approaches, the complete symbolic simulation works more efficiently,
and therefore can provide correctness proofs for larger systems, which is one
of the most challenging tasks, due to the ever increasing complexity.</p>
master thesis, Vladimir Herdt presents a novel approach, called complete
symbolic simulation, for a more efficient verification of
much larger (non-terminating) SystemC programs. The
approach combines symbolic simulation with stateful model checking and allows
to verify safety properties in (cyclic) finite state spaces, by exhaustive
exploration of all possible inputs and process schedulings. The state explosion
problem is alleviated by integrating two complementary reduction techniques. Compared
to existing approaches, the complete symbolic simulation works more efficiently,
and therefore can provide correctness proofs for larger systems, which is one
of the most challenging tasks, due to the ever increasing complexity.</p>
<p>Verification of Systems .- Introduction to Formal Verification of
SystemC Models.- Symbolic Model Checking with Partial Order Reduction.- Efficient
Symbolic State Matching using State Subsumption.- Heuristic Approaches for
Symbolic State Matching.- Evaluation of Proposed Techniques.</p>
SystemC Models.- Symbolic Model Checking with Partial Order Reduction.- Efficient
Symbolic State Matching using State Subsumption.- Heuristic Approaches for
Symbolic State Matching.- Evaluation of Proposed Techniques.</p>
<p>Vladimir Herdt is working as Research
Assistant in the Group of Computer Architecture at the University of Bremen,
where he is pursuing his PhD degree. <b></b></p>
Assistant in the Group of Computer Architecture at the University of Bremen,
where he is pursuing his PhD degree. <b></b></p>
<p>In his
master thesis, Vladimir Herdt presents a novel approach, called complete
symbolic simulation, for a more efficient verification of
much larger (non-terminating) SystemC programs. The
approach combines symbolic simulation with stateful model checking and allows
to verify safety properties in (cyclic) finite state spaces, by exhaustive
exploration of all possible inputs and process schedulings. The state explosion
problem is alleviated by integrating two complementary reduction techniques. Compared
to existing approaches, the complete symbolic simulation works more efficiently,
and therefore can provide correctness proofs for larger systems, which is one
of the most challenging tasks, due to the ever increasing complexity.</p><p><b>Contents</b></p><p></p><p><ul><li>Verification of Systems<br></li><li>Introduction to
Formal Verification of SystemC Models<br></li><li>Symbolic Model
Checking with Partial Order Reduction</li><li>Efficient Symbolic
State Matching using State Subsumption</li><li>Heuristic Approaches
for Symbolic State Matching</li><li>Evaluation of
Proposed Techniques</li></ul></p><p></p><p> <b>Target
Groups</b><br></p><p><ul><li>Lecturers and Students
of Computer Sciences and Electrical Engineering</li><li>Hardware Designers
and Verification Engineers using SystemC</li></ul></p><p><b>The
Author</b><br></p><p>Vladimir Herdt is working as Research
Assistant in the Group of Computer Architecture at the University of Bremen,
where he is pursuing his PhD degree. <b></b></p><p> </p><p>
<br></p><b></b><p></p>
master thesis, Vladimir Herdt presents a novel approach, called complete
symbolic simulation, for a more efficient verification of
much larger (non-terminating) SystemC programs. The
approach combines symbolic simulation with stateful model checking and allows
to verify safety properties in (cyclic) finite state spaces, by exhaustive
exploration of all possible inputs and process schedulings. The state explosion
problem is alleviated by integrating two complementary reduction techniques. Compared
to existing approaches, the complete symbolic simulation works more efficiently,
and therefore can provide correctness proofs for larger systems, which is one
of the most challenging tasks, due to the ever increasing complexity.</p><p><b>Contents</b></p><p></p><p><ul><li>Verification of Systems<br></li><li>Introduction to
Formal Verification of SystemC Models<br></li><li>Symbolic Model
Checking with Partial Order Reduction</li><li>Efficient Symbolic
State Matching using State Subsumption</li><li>Heuristic Approaches
for Symbolic State Matching</li><li>Evaluation of
Proposed Techniques</li></ul></p><p></p><p> <b>Target
Groups</b><br></p><p><ul><li>Lecturers and Students
of Computer Sciences and Electrical Engineering</li><li>Hardware Designers
and Verification Engineers using SystemC</li></ul></p><p><b>The
Author</b><br></p><p>Vladimir Herdt is working as Research
Assistant in the Group of Computer Architecture at the University of Bremen,
where he is pursuing his PhD degree. <b></b></p><p> </p><p>
<br></p><b></b><p></p>
Study in Computer Sciences Includes supplementary material: sn.pub/extras
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